1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to the techniques for reducing chip-package interactions caused by thermal mismatch between the chip and the package substrate.
2. Description of the Related Art
Semiconductor devices are typically formed on substantially disc-shaped substrates made of any appropriate material. The majority of semiconductor devices including highly complex electronic circuits are currently, and in the foreseeable future will be, manufactured on the basis of silicon, thereby rendering silicon substrates and silicon-containing substrates, such as silicon-on-insulator (SOI) substrates, viable base materials for forming semiconductor devices, such as microprocessors, SRAMs, ASICs (application specific ICs), systems on chip (SoC) and the like. The individual integrated circuits are arranged in an array on the wafer, wherein most of the manufacturing steps, which may involve several hundred and more individual process steps in sophisticated integrated circuits, are performed simultaneously for all chip areas on the substrate, except for photolithography processes, metrology processes and packaging of the individual devices after dicing the semiconductor substrate. Thus, economic constraints drive semiconductor manufacturers to steadily increase the substrate dimensions, thereby also increasing the area available for producing actual semiconductor devices and thus increasing production yield.
In addition to increasing the substrate area, it is also important to optimize the utilization of the substrate area for a given substrate size so as to actually use as much substrate area as possible for semiconductor devices and/or test structures that may be used for process control. In an attempt to maximize the useful surface area for a given substrate size, the feature sizes of circuit elements are steadily scaled down. Due to this ongoing demand for shrinking the feature sizes of highly sophisticated semiconductor devices, copper, in combination with low-k dielectric materials, has become a frequently used alternative in the formation of so-called interconnect structures comprising metal line layers and intermediate via layers that include metal lines as intra-layer connections and vias as inter-layer connections, which commonly connect individual circuit elements to provide the required functionality of the integrated circuit. Typically, a plurality of metal line layers and via layers stacked on top of each other is necessary to realize the connections between all internal circuit elements and I/O (input/output), power and ground pads of the circuit design under consideration.
For extremely scaled integrated circuits, the signal propagation delay is no longer limited by the circuit elements, such as field effect transistors and the like, but is limited, owing to the increased density of circuit elements requiring an even more increased number of electrical connections, by the close proximity of the metal lines, since the line-to-line capacitance is increased and the conductivity of the lines is reduced due to a reduced cross-sectional area. For this reason, traditional dielectrics, such as silicon dioxide (k>3.6) and silicon nitride (k>5), are replaced by dielectric materials having a lower permittivity, which are, therefore, also referred to as low-k dielectrics, having a relative permittivity of 3 or less. However, the density and mechanical stability or strength of the low-k materials may be significantly less compared to the well-approved dielectrics silicon dioxide and silicon nitride. As a consequence, during the formation of the metallization system and any subsequent manufacturing processes of integrated circuits, production yield may depend on the mechanical characteristics of sensitive dielectric materials, such as low-k dielectric layers, and their adhesion to other materials.
In addition to the problems of reduced mechanical stabilities of advanced dielectric materials having a dielectric constant of 3.0 and significantly less, device reliability may also be affected by these materials during operation of sophisticated semiconductor devices due to an interaction between a chip and the package, wherein this interaction is caused by a thermal mismatch of the corresponding thermal expansion of the different materials. For instance, in the fabrication of complex integrated circuits, increasingly, a contact technology may be used for connecting the package substrate to the chip, which is known as flip chip packaging technique. Contrary to the well-established wire bonding techniques in which appropriate contact pads may be positioned at the periphery of the very last metal layer of the chip, which may be connected to corresponding terminals of the package by a wire, in the flip chip technology, a respective bump or pillar structure may be formed on the last metallization layer, for instance comprised of a solder material, which may be brought into contact with respective contact pads of the package. Thus, after reflowing the bump material, a reliable electrical and mechanical connection may be established between the last metallization layer and the contact pads of the package substrate. In this manner, a very large number of electrical connections may be provided across the entire chip area of the last metallization layer with reduced contact resistance and parasitic capacitance, thereby providing the IO (input/output) capabilities as required for complex integrated circuits, such as CPUs, storage memories and the like. During the corresponding process sequence for connecting the bump structure with a package substrate, a certain degree of pressure and/or heat may be applied to the composite device so as to establish a reliable connection between each of the bumps formed on the chip and the bumps or pads that may be provided on the package substrate. The thermally or mechanically induced stress may, however, also act on the lower lying metallization layers, which may typically include low-k dielectrics or even ultra low-k (ULK) dielectric materials, thereby significantly increasing the probability of creating defects by delamination of these sensitive materials due to reduced mechanical stability and adhesion to other materials.
Moreover, during operation of the composite semiconductor device, i.e., the semiconductor chip attached to the corresponding package substrate, significant mechanical stress may also occur due to a significant mismatch in the thermal expansion behavior of the silicon-based semiconductor chip and the package substrate, since, in volume production of sophisticated integrated circuits, economic constraints typically require the usage of specified substrate materials for the package, such as organic materials, which may typically exhibit a different thermal conductivity and a different coefficient of thermal expansion compared to the silicon chip. Consequently, a premature failure of the metallization system may occur.
With reference to FIGS. 1a-1b, a typical chip-package interaction will be described in more detail.
FIG. 1a schematically illustrates a cross-sectional view of an integrated circuit 100 comprising a semiconductor die or chip 150 connected to a package substrate 170, which is substantially comprised of an organic material, such as a polymer material and the like. As discussed above, in total, the semiconductor chip 150 has a coefficient of thermal expansion (CET) that is significantly different from the CET of the package substrate 170, that is, typically, the CET of the package substrate 170 may be greater compared to the silicon-based semiconductor die 150. The semiconductor die 150 typically comprises a substrate 151, for instance in the form of a silicon substrate or an SOI substrate, depending on the overall configuration of the circuit layout and performance of the integrated circuit 100. Moreover, a silicon-based semiconductor layer 152 is provided “above” the substrate 151, wherein the semiconductor layer 152 comprises a very large number of circuit elements, such as transistors, capacitors, resistors and the like, as are required for implementing the desired functionality of the integrated circuit 100. As previously discussed, the ongoing shrinkage of critical dimensions of circuit elements has resulted in critical dimensions of transistors on the order of magnitude of 50 nm and significantly less in presently available sophisticated semiconductor devices that are produced by volume production techniques.
The semiconductor chip 150 further comprises a metallization system 153, which, in advanced semiconductor devices, comprises a plurality of metallization layers, i.e., device levels in which metal lines and vias are embedded in an appropriate dielectric material. As explained above, at least a portion of the corresponding dielectric materials used in the various metallization layers of the metallization system 153 are comprised of materials of reduced mechanical stability in order to provide as low a parasitic capacitance of adjacent metal lines as possible. Moreover, the device 150 comprises a bump structure 155 that is appropriately connected to the metallization system 153, wherein the corresponding bumps or metal pillars may be provided as a part of the last metallization layer of the system 153, for instance in the form of a solder material, metal pillars or a combination thereof. On the other hand, the package substrate 170 comprises appropriately positioned and dimensioned contact pads of a contact structure 175, which may be brought into contact with the corresponding bumps of the structure 155 in order to establish respective mechanical and electrical connections upon applying heat and mechanical pressure. Furthermore, the package substrate 170 may comprise any appropriate conductive lines (not shown) in order to connect the bump structure 155 with appropriate terminals, which thus establish an electrical interface to other peripheral components, such as a printed wiring board and the like.
During operation and also during the process of forming the composite device 100 from the semiconductor die 150 and the package substrate 170, heat is generated in the semiconductor chip 150 or is transferred thereto, which may finally result in a significant interaction between the semiconductor die 150 and the package substrate 170, for instance after reflowing and hardening of the bumps in the structure 155, which may thus result in significant shear forces due to the mismatch in the CETs of the device 150 and 170. For example, at the interface between the semiconductor die 150 and the package substrate 170, that is, in particular, the bump structure 155 and the metallization system 153 may experience significant mechanical stress forces caused by the thermal mismatch during assembly and operation of the device 100. Due to the reduced mechanical stability and the reduced adhesion of sophisticated dielectric materials, corresponding defects typically occur, which thus affect the overall reliability and also production yield when operating or manufacturing the integrated circuit 100. For example, a certain degree of thermally induced stress, as indicated by 103, may occur in the package substrate 170, thereby resulting in a certain degree of bending or bowing, indicated by 176, due to any temperature gradients and the increased CET of the material 170 compared to the semiconductor die 150.
FIG. 1b schematically illustrates an enlarged view of a portion of the metallization system 153 during a typical situation when operating the integrated circuit 100 or when assembling the device 100 in a final phase, when the solder bumps increasingly harden after reflowing of any solder material. As illustrated, the metallization system 153 comprises the plurality of metallization layers, wherein, for convenience, two metallization layers 154 and 156 are illustrated. For example, the metallization layer 156 comprises a dielectric material 156A, in which corresponding metal lines 156B and vias 156C are embedded. Similarly, the metallization layer 154 comprises a dielectric material 154A and respective metal lines 154B and vias 154C. As previously explained, at least some of the metallization layers in the metallization system 153 comprise a sensitive dielectric material in the form of a low-k dielectric material or a ULK material, which exhibits a significantly reduced mechanical stability compared to other dielectrics, such as silicon nitride, silicon carbide, nitrogen-containing silicon carbide, which may frequently be used as etch stop or capping layers provided between the individual metallization layers 154, 156. Consequently, during operation or assembly of the integrated circuit 100, due to the different behavior with respect to thermal expansion, a significant mechanical stress is transferred into the metallization layers 156, 154, as indicated by 103. The stress 103 is also present in the package substrate 170 (FIG. 1a), and may result in a material deformation, as indicated by 176 (FIG. 1a). On the other hand, the mechanical stress 103 in the metallization system 153 may induce a more or less pronounced strained state that results in the creation of certain defects 154D, 156D, which in turn may finally result in a certain degree of delamination, since typically the adhesion and mechanical stability of ULK dielectric materials is reduced compared to conventional dielectric materials, as discussed above. Consequently, the resulting delamination may finally result in a premature failure of the metallization system 153 or in an initial failure of the metallization system, thereby contributing to reduced production yield and reduced overall reliability of the integrated circuit 100 (FIG. 1a).
The problem of reduced reliability and reduced production yield of sophisticated metallization systems is even further exacerbated in advanced process technologies in which the dielectric constant of the low-k dielectric materials is to be further reduced, while at the same time the dimensions of the corresponding chip areas are increased in order to incorporate more and more functions into the integrated circuits. On the other hand, the increased complexity of the overall circuit layout may also require an increased number of stacked metallization layers, as previously explained, which may additionally result in a reduced overall mechanical stability of the metallization system. Furthermore, the usage of lead-free materials in the bump structure 155 (FIG. 1a) may result in an increased mechanical coupling of the package substrate 170 and the semiconductor chip 150, thereby resulting in even higher mechanical stress, since, typically, lead-free contact assemblies are less resilient compared to lead-containing solder materials.
For these reasons, in conventional approaches, the overall size of the semiconductor die has to be restricted to appropriate dimensions in performance driven metallization systems so as to maintain the overall mechanical stress components at an acceptable level. In other cases, the number of metallization layers may be restricted, thereby also reducing the packing density and/or complexity of the circuit layout. In still other conventional approaches, less sophisticated dielectric materials are used in order to enhance the overall mechanical stability, thereby, however, sacrificing performance of the integrated circuits.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.